ordec.extlibrary — Working with external design data

class ordec.extlibrary.ExtLibrary

TODO: Document me

read_gds(gds_fn: str, layers: LayerStack)

TODO: Document me

read_yosys_json(json_data: dict)

Add schematic(s) from Yosys JSON data.

Parameters:

json_data – Yosys JSON as dict.

read_verilog(verilog: str)

Add schematic from a synthesized Verilog netlist.

Parameters:

verilog – Synthesized Verilog netlist as string.

read_spice(path, device_map: dict)

Add schematic(s) from a SPICE subcircuit netlist file.

Each .subckt becomes a schematic; device instances are mapped to ORDeC leaf cells via device_map (model name -> DeviceMapping).

Symbols are auto-generated from the subckt port lists as a fallback only: a symbol already registered by another reader (e.g. read_lef, which also provides pin directions) takes precedence. Call read_lef before read_spice to get correct pin directions.

Parameters:

• path – Filesystem path to a SPICE netlist file.

• device_map – Mapping of SPICE model name to ordec.schematic.spice_in.DeviceMapping.