`ordec.lib.ihp130` — IHP SG13G2 technology

This cell library provides part of the IHP Open PDK.

Substrate handling in LVS

All SG13G2 resistors (Rsil, Rppd, Rhigh) have a third pin bn connecting the device’s bulk/substrate node. In LVS netlists, the resistors are emitted as three-terminal SPICE elements, so substrate connectivity is part of the layout vs. schematic comparison.

On the layout side, the SG13G2 LVS deck merges the resistors’ bulk into a single chip-wide substrate (pwell) net. For hierarchical designs, this has the following consequences:

Every cell whose layout contains a resistor (directly or in a subcell) is extracted with an additional, implicit pin for the propagated substrate net — even though the cell’s layout draws no substrate pin shape.
For LVS to pass, the schematic of each such cell needs a matching substrate port (named sub by convention) wired to the bn pins of all resistors and propagated down the hierarchy. Within the hierarchy, KLayout matches the extracted substrate pin against this port topologically; subcell layouts need neither a pin shape nor a label for it.
The top cell is the exception: top-level pins are compared by name, so the top layout must materialize the substrate connection explicitly. Place a substrate tap (Ptap) and attach a labeled Metal1 pin to it (see cell C_Hier in tests/lib/lvs_example_hier.ord for a working example).

Approaches that do not work:

A pin label directly on the substrate region: the deck’s connectivity setup attaches no text/pin layer to the substrate, so such labels are ignored and the top-level substrate pin remains unnamed.
Netlisting bn as a global net (.global sub!) instead of explicit sub ports: the subcells then match, but the top-level pin comparison fails because the layout’s implicit substrate pin has no name to match against SUB!.

Cells

class ordec.lib.ihp130.Cmim(*args, **kwargs)

Fixed SG13G2 MIM capacitor.

escaped_name()

ngspice_current_pins()

ngspice_save_params() → list[str]: Return device parameter names to save via ngspice.

ic: Rational

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational

layout

m: int

symbol

w: Rational

class ordec.lib.ihp130.Nmos(*args, **kwargs)

escaped_name()

ngspice_current_pins()

ngspice_save_params()

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational: Length

layout

m: int: Multiplier, i. e. number of devices with separate Activ areas in parallel)

model_name = 'sg13_lv_nmos'

ng: int: Number of gate fingers

symbol

w: Rational: Width

class ordec.lib.ihp130.Ntap(*args, **kwargs)

escaped_name()

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational: Length

layout

w: Rational: Width

class ordec.lib.ihp130.Pmos(*args, **kwargs)

escaped_name()

ngspice_current_pins()

ngspice_save_params()

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational: Length

layout

m: int: Multiplier, i. e. number of devices with separate Activ areas in parallel)

model_name = 'sg13_lv_pmos'

ng: int: Number of gate fingers

symbol

w: Rational: Width

class ordec.lib.ihp130.Ptap(*args, **kwargs)

escaped_name()

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational: Length

layout

w: Rational: Width

class ordec.lib.ihp130.Rhigh(*args, **kwargs)

High-resistive polysilicon resistor (high sheet resistance). For the substrate pin bn and its LVS handling, see Substrate handling in LVS.

escaped_name()

ngspice_current_pins()

ngspice_save_params() → list[str]: Return device parameter names to save via ngspice.

b: int

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational

layout

m: int

model_name = 'rhigh'

ps: Rational

symbol

w: Rational

class ordec.lib.ihp130.Rppd(*args, **kwargs)

Unsalicided p+ polysilicon resistor (medium sheet resistance). For the substrate pin bn and its LVS handling, see Substrate handling in LVS.

escaped_name()

ngspice_current_pins()

ngspice_save_params() → list[str]: Return device parameter names to save via ngspice.

b: int

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational

layout

m: int

model_name = 'rppd'

ps: Rational

symbol

w: Rational

class ordec.lib.ihp130.Rsil(*args, **kwargs)

Salicided polysilicon resistor (low sheet resistance). For the substrate pin bn and its LVS handling, see Substrate handling in LVS.

escaped_name()

ngspice_current_pins()

ngspice_save_params() → list[str]: Return device parameter names to save via ngspice.

b: int

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

l: Rational

layout

m: int

model_name = 'rsil'

ps: Rational

symbol

w: Rational

class ordec.lib.ihp130.SG13G2(*args, **kwargs)

escaped_name()

default_routing_spec

instances_lock = <unlocked _thread.RLock object owner=0 count=0>

layers

ordec.lib.ihp130.run_drc(l: Layout, variant='maximal', use_tempdir: bool = True)

ordec.lib.ihp130.run_lvs(layout: Layout, symbol: Symbol, use_tempdir: bool = True) → LvsReport

Run LVS (Layout vs. Schematic) check.

Parameters:

layout – The Layout to check.
symbol – The Symbol containing the reference schematic.
use_tempdir – If True, use a temporary directory for intermediate files.